In a typical integrated circuit (IC), clock signals drive large loads, and typically need to have very tight tolerance, which results in large drive strengths of the buffers in, e.g., the clock paths. As application-specific integrated circuit (ASIC) design evolved, IC designers worked to ensure that clock signals for numerous latches of an IC arrive substantially at the same time. In the succeeding generations of ASIC designs, tools to balance clock path delays and circuits such as Clock Generation Phase-Locked-Loops have been developed to ensure high performance logic operation. However, as the number of sequential elements within today's ASICs increases, the instantaneous noise current associated with the simultaneous propagation of clock signals (clocks) through balanced clock trees to thousands of latches has also increased, compromising data integrity and limiting functional performance of ASICs.
Efforts have been made to solve the above noise problem. Recently, Haar et al. (U.S. patent application Ser. No. 10/904,397) provide a method for converting a latch driven by a globally propagated clock to a latch with a phase-shifted, locally-generated clock such that the peak noise event caused by clock propagation may be reduced. However, because Haar et al. operate on an ASIC developed with known placement and timing tools and can only reduce noise at latch points with positive slacks, the amount of noise reduction may be limited.
As such, there is a need in the art to further reduce clock noise within an IC, which is not limited by the timing slacks of clocked elements. The present state of the art technology does not provide a satisfactory solution to this need.